1. Field of the Invention
The present invention relates to a ferroelectric random access memory (RAM) device.
2. Description of the Prior Arts
In general, a procedure of reading an information stored in the ferroelectric RAM device is as follows. First, if a word line is selected, a bit line has voltage of V0 or V1, which are different from each other, according to an information of 0 or 1 stored in the memory cell. Since the voltage V0 or V1 of the bit lines is small, it must be amplified by means of a sense amplifier. To amplify the voltage V0 or V1 of the bit lines, a reference voltage Vref having a value between V0 and V1 and applied to one bit line is necessary.
That is, information of the cell is sensed by comparing the reference voltage Vref applied to the bit line with the voltage V0 or V1 of other bit line by means of the sense amplifier. As a result, it is possible to sense whether the information of the cell is 0 or 1. Also, the sensing margin is required to compare the reference voltage Vref and the voltage of the bit line, and the sensing margin is varied according to an electric charge of the reference cell used in a reference voltage generator.
However, in the prior art, since information of 0 and 1 are fixedly stored in two reference cells, respectively, the number of using the reference cell is more increased than the number of using the memory cell so that the electric charge of the reference cell is lower than that of the memory cell. The decrease of the electric charge brings about the change in the voltage and has a problem in that the securance of sensing margin is difficult.
Details of the prior art will be described with reference to FIG. IA, FIG. 1B and FIG. 1C.
FIG. 1A through FIG. 1C are circuit diagrams illustrating a prior art ferroelectric memory device. The procedure of fixedly storing an information of 0 and 1 in reference cells C1 and C2 of a reference voltage generating circuit 11 is as follows.
When a reference word line RWL is selected and potential of a reference write terminal R-write becomes a high level, a first transfer gate T11 and a second transfer gate T12 are turned on by the potential of the reference write terminal R-write and an output of a second inverter G12. Accordingly, voltage Vdd is inverted by a first inverter G11 and then is applied to a reference bit line RBL through the first transfer gate T11, and the voltage Vdd is also applied to a reference bit line bar RBLB through the second transfer gate T12 as shown in FIG. 1C.
As a result, a voltage of low state is applied to the first reference cell C1 through the first transfer gate T11 so that an information of 0 is stored in the first reference cell C1. Also, a voltage of high state is applied to the second reference cell C2 through the second transfer gate T12 so that an information of 1 is stored in the second reference cell C2.
The procedure of reading the information stored in the ferroelectric memory is described below.
As shown in FIG. 1B, if a word line WL0 becomes a high state by a decoder 14, transistors Q11 and Q12 are turned on (assuming that the information of 0 is stored in a memory cell C11 and the information of 1 is stored in a memory cell C12 among a memory cell array 12). A precharge bit line PBL of FIG. 1A becomes a high state, bit lines BL0, BL0.sub.-- bar, BL1 and BL1.sub.-- bar are grounded. Also, a precharge reference line PRL of FIG. 1C becomes high state, reference bit lines RBL and RBLB are grounded.
Electric charges stored in the memory cells C11 and C12 are transferred to the bit lines BL0 and BL1 according to a signal applied to a word line WL0 and a signal applied to a plate terminal. In addition, the information of 0 and 1 fixedly stored in the first and second reference cells C1 and C2 of the reference voltage generation circuit 11, respectively are transferred to the reference bit lines RBL and RBLB by applying a signal having a high level to the reference word line RWL and reference plate line RPL. An equalization reference line EQ.sub.-- RL becomes high state so that the reference bit lines RBL and RBLB are equalized. The equalized voltages are transferred to the bit lines BL0.sub.-- bar and BL1.sub.-- bar according to a high state signal applied to a terminal DTGN. Voltage transferred to the bit lines BL0.sub.-- bar and BL1.sub.-- bar have an intermediate value between the voltages of the bit lines BL0 and BL1. That is, since the information of 0 is stored in the cell C11, the bit line BL0 has a voltage which is lower than a voltage of the bit line BL0.sub.-- bar, also since the information of 1 is stored in the cell C12, the bit line BL1 has a voltage which is higher than a voltage of the bit line BL1.sub.-- bar.
The difference between the two voltages is sensed by a sense amplifier 13 when potential of a terminal read 1 becomes a high state after Vdd is applied to a terminal sap and a terminal san is grounded. Data of a low level is transferred to a terminal data 0 and data of a high level is transferred to a terminal data 1 and they are sent to an output buffer. To restore the original value before the reading out operation to the memory cells, the terminals read 1, plate, sap and san become a low level. Thereafter, if the reference bit lines RBL and RBLB are grounded by applying a high state to the precharge reference line PRL, the potential of reference word line RWL and the word line WL0 are transformed into a low state, then one cycle for reading out the information stored in the memory cells is completed.
The restoring operation of the reference cells is as follows.
Data before reading, that is, 0 and 1 are stored in the cells C1 and C2 by means of a signal applied to the reference write terminal Write R.sub.-- write. Then signals applied to the terminals RPL and R.sub.-- write are transformed into low state. Then, if the reference bit line RBL is to be ground by applying a high state signal to the precharge reference line PRL and the potential of reference word line RWL is transformed into a low state, then one cycle of the operation of the reference cells is completed.
However, since one reference voltage generation circuit 11 is used on one bit line to which a plurality of memory cells are arrayed in the prior art, the number of using the reference cell is increased by the number of memory cell arrays 12. That is, since 0 and 1 are fixedly stored in two reference cells C1, C2, the amount of electric charge is decreased according to the increase in the number of using the reference cell and it is difficult to secure the sensing margin according to the change in reference voltage, whereby the reliability in the device is degraded.